This invention relates to multilayer ceramic substrates particularly adapted for mounting and interconnecting semiconductor chips.
The application wherein the instant invention has its greatest utility is in a multi-chip module for use in data processing equipment. This application and the then state-of-the-art multi-chip module, as well as the method of fabricating the multilayer ceramic (MLC) substrate is described by A. J.. Blodgett and D. R. Barbour in an article entitled "Thermal Conduction Module: A High Performance Multi-layer Ceramic Package" published in the IBM Journal of Research and Development, Vol. 26, No. 1, January 1982, page 30 et seq.
The foregoing highlights the cycle time reduction achieved by the thermal conduction model over prior methods of interconnecting circuit components.
A further dissertation on multilayer ceramic fabrication can be found in the article by W. G. Berger and C. W. Weigel entitled "Multi-Layer Ceramics Manufacturing" appearing in the IBM Journal of Research and Development, Vol. 27 No. 1, Page 11, et seq.
The circuit density and quantity of the discrete circuit elements in a chip is ever increasing, as is the speed of operation of the chips. Derivatively, the so-called "footprint" density of the chip i.e., the number of chip circuit pads per unit area for connection to the multilayer ceramic (MLC) substrate, is increasing. This necessitates a corresponding increase in the "footprint" density of the complementary pad pattern of the MLC substrate. The increase in the number of pads per chip requires an increase in the number of inter-chip conductors.
While one can increase the number of layers in the MLC substrate to provide more complex interconnecting metal patterns, this is not without penalty. Any increase in conductor length increases circuit delays. Adding layers increases fabrication difficulties. It does not solve the footprint density problem unless there can be found a means for depositing a finer, more closely spaced metallization pattern on the MLC substrate.
Prior art MLC substrates utilize processed metal powders, i.e. metal particles that are screened and subsequently sintered to form metal patterns on the respective lamina, interconnected by sintered metal in via holes penetrating the laminae at selected positions. The metal patterns were applied to the green sheet laminae by a screening and subsequent sintering process. This process is incapable of producing very small closely spaced conductors, and cannot produce the complementary footprint for the advanced generation of chips. Even if it were capable, metallurgy formed by screening processes or other metal particle processes, and subsequently sintered has too high of a resistivity to permit the use of small area conductors.
The problem of resistivity was partially addressed by Ahn et al. in U.S. Pat. No. 3,852,877 wherein they formed sintered metal-lined "burrows" in the fired MLC substrate and subsequently filled the burrows with molten metal of high conductivity, such as with copper, to provide the interconnecting metal pattern. Ahn, et al describes their invention as "the formation of metallized capillaries within a multilayer ceramic circuit board, which capillaries are subsequently filled with a high conductivity metal".
Since the capillaries are lined with a refractory metal and filled with molten metal after the substrate is fired, the conductive network consisted of solid metal and sintered refractory metal. Thus, the density of the conductive network was not only limited by the screening process, but also by the necessity of having lined capillaries through which the molten metal could subsequently flow. The via holes and metal paste pattern in one of the described embodiments were 10 mils. In another embodiment a porous capillary, as opposed to a lined capillary, received the molten metal.
If fine, closely-spaced, non-screened metal conductors are to be used in a MLC substrate, the metal must be deposited by a process other than screening and the metal must have a melting temperature higher than the sintering temperature of the ceramic. The metal must also have a low resistivity. The chosen ceramic must either have zero shrinkage upon firing or be restrained from shrinkage. The above-cited co-filed patent application describes various ceramics and methods for restraining shrinkage during firing, as does U.S. Pat. No. 3,879,509.
The use of glass ceramics which can be fired at temperatures lower than the melting points of high conductivity metals for MLC substrates has been discussed at length in U.S. Pat. Nos. 4,234,367; 4,301,324; 4,340,436; and 4,413,061. Glass ceramics not only have this desirable property, but also they have a low dielectric constant, high flexural strength and have a low thermal coefficient of expansion, all most desirable for high speed electronic applications.
The techniques for producing microscopically small metallized patterns on semiconductor chips is well known in the art. If these could be adapted for producing the metal patterns on the MLC laminae, one could not only achieve the dense footprint, but the fine, closely-spaced conductors. However, these semiconductor device metallization processes are not suited for directly metallizing the greensheet laminae of an MLC substrate. The greensheets do not have a sufficiently smooth surface to receive the fine close-spaced metal patterns directly without risk of rupture or alteration of the critical inter-conductor spacing. Also, any metallization process involving subatmospheric pressure would be severely impacted by organic outgassing of binder materials, changing greensheet composition (for example, making sheets stiff), and contaminating the processing system.
It is therefore necessary to find an alternative to depositing the fine metal pattern directly on the greensheet.